1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a dynamic random access memory (DRAM) that allows reduction in power consumption during a refresh operation.
2. Description of the Background Art
FIG. 15 is a block diagram representing an arrangement of a control circuit 508 for performing a role activation timing control in a conventional synchronous DRAM.
Referring to FIG. 15, control circuit 508 receives control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS and internal bank address signals int.BA less than 0:1 greater than , and outputs row address decode signals RADE less than 0:3 greater than , word line trigger signals RXT less than 0:3 greater than , sense amplifier activating signals S0N less than 0:3 greater than , and an internal address Q for refresh operation. In addition, a prefix xe2x80x9cZxe2x80x9d indicates that the signal is an L-active signal, i.e. a signal whose active state is at the low level.
Control circuit 508 includes a command decode circuit 552 for receiving control signals int.ZRAS, int. ZCAS, int.ZWE, and int.ZCS and detecting a command from a combination of these signals, and a refresh control unit 554 for performing refresh control according to an output from command decode circuit 552.
Control circuit 508 further includes a bank selecting unit 556 for selecting the output of command decode circuit 552 according to internal bank address signals int.BA less than 0:1 greater than , and a bank selecting unit 560 for selecting an output of refresh control unit 554 according to internal bank address signals int.BA less than 0:1 greater than .
Control circuit 508 further includes an NOR circuit 558 for receiving signals ACT less than 0:3 greater than  output from bank selecting unit 556 and signals AREF less than 0:3 greater than  output from bank selecting unit 560 and outputting signals ZRASE less than 0:3 greater than , and a control circuit 562 for outputting row address decode signals RADE less than 0:3 greater than , word line trigger signals RXT less than 0:3 greater than , and sense amplifier activating signals S0N less than 0:3 greater than  according to signals AREF less than 0:3 greater than  and signals ZRASE less than 0:3 greater than .
Command decode circuit 552 includes an active command decoder 572 for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect an active command, an auto-refresh command decoder 574 for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect an auto-refresh command, and a self-refresh command decoder 576 for receiving control signals int.ZRAS, int.ZCAS, int.ZWE, and int.ZCS to detect a self-refresh command.
Refresh control unit 554 includes a self-refresh timer 580 for activating a signal RINGOUT at certain intervals according to a signal SREF output from self-refresh command decoder 576, a refresh operation control circuit 582 for outputting a signal AREFS according to an output from auto-refresh command decoder 574 and a signal RINGOUT, a 1 shot pulse generating circuit 584 for outputting a signal REFA according to signal AREFS, and an internal address counter 586 for counting internal address Q during a refresh operation according to signal REFA.
Control circuit 562 includes a row-related control circuit 564 for outputting a row address decode signal RADE less than 0 greater than , a word line trigger signal RXT less than 0 greater than , and a sense amplifier activating signal S0N less than 0 greater than  according to a signal ZRASE less than 0 greater than , a row-related control circuit 566 for outputting a row address decode signal RADE less than 1 greater than , a word line trigger signal RXT less than 1 greater than , and a sense amplifier activating signal S0N less than 1 greater than  according to a signal ZRASE less than 1 greater than , a row-related control circuit 568 for outputting a row address decode signal RADE less than 2 greater than , a word line trigger signal RXT less than 2 greater than , and a sense amplifier activating signal S0N less than 2 greater than  according to a signal ZRASE less than 2 greater than , and a row-related control circuit 570 for outputting a row address decode signal RADE less than 3 greater than , a word line trigger signal RXT less than 3 greater than , and a sense amplifier activating signal S0N less than 3 greater than  according to a signal ZRASE less than 3 greater than .
FIG. 16 is a circuit diagram showing an arrangement of row-related control circuit 564 in FIG. 15.
Referring to FIG. 16, row-related control circuit 564 includes a signal generating unit 632 for outputting a row address decode signal RADE according to a signal ZRASE, a signal generating unit 634 for outputting a signal RXT according to a signal ZRASE and signal RADE, and a signal generating unit 636 for outputting sense amplifier activating signals S0N, /S0N according to signal RXT.
Signal generating unit 632 includes a delay stage 640 for delaying sense amplifier activating signal S0N, an inverter 638 for receiving and inverting signal ZRASE, and an OR circuit 642 for receiving outputs from delay stage 640 and inverter 638 and outputting signal RADE.
Delay stage 640 includes inverters 644 and 646 connected in series for receiving sense amplifier activating signal S0N.
Signal generating unit 634 includes an inverter 648 for receiving and inverting signal ZRASE, a delay stage 650 for receiving and delaying an output from inverter 648, a delay stage 652 for delaying signal RADE, and an AND circuit 654 for receiving outputs from delay stages 650 and 652 and outputting signal RXT.
Delay stage 650 includes inverters 656 and 658 connected in series for receiving the output from inverter 648. Delay stage 652 includes inverters 660 and 662 connected in series for receiving signal RADE.
Signal generating unit 636 includes a delay stage 664 for receiving and delaying signal RXT and outputting sense amplifier activating signal S0N, and an inverter 676 for receiving and inverting sense amplifier activating signal S0N and outputting sense amplifier activating signal /S0N.
Delay stage 664 includes inverters 678 and 680 connected in series for receiving signal RXT.
FIG. 17 is a circuit diagram representing the arrangement of auto-refresh command decoder 574 and refresh operation control circuit 582 in FIG. 15.
Referring to FIG. 17, auto-refresh command decoder 574 includes an inverter 692 for receiving and inverting a signal int.ZRAS, an inverter 694 for receiving and inverting a signal int.ZCAS, and an NAND circuit 696 for receiving outputs from inverters 692 and 694 and a signal int.ZWE.
Refresh operation control circuit 582 receives an output from NAND circuit 696 at a node N11.
Refresh operation control circuit 582 includes an inversion delay circuit 698 having an input connected to node N11 and an output connected to a node N13, an NOR circuit 700 having one input connected to node N11, the other input connected to node N13, and an output connected to a node N12, and an NOR circuit 702 for receiving signal RINGOUT and an output from NOR circuit 700. Inversion delay circuit 698 includes inverters 710, 712, and 714 connected in series.
Refresh operation control circuit 582 further includes a latch circuit 704 having the data set according to an output of NOR circuit 702, a delay stage 706 for delaying an output from latch circuit 704, and an inverter 708 for inverting an output from delay stage 706.
Latch circuit 704 includes an NAND circuit 716 having one input receiving the output from NOR circuit 702 and the other input connected to a node N15 for outputting a signal AREFS, and an NAND circuit 718 having one input receiving signal AREFS, the other input connected to a node N14, and an output node connected to node N15.
Delay stage 706 includes inverters 720 and 722 connected in series for receiving signal AREFS.
FIG. 18 is an operational waveform chart related to a description of an auto-refresh operation of a conventional DRAM.
Referring to FIG. 18, signals ext.ZRAS, ext.ZCAS, ext.ZWE, CKE, ext.CLK, and ext.ZCS are input signals externally supplied to the DRAM. A signal ext.ZRAS is row address strobe signal, and a signal ext.ZCAS is a column address strobe signal.
In addition, a signal AREF is an auto-refresh signal that is set to the logic high or H level during an auto-refresh operation, a signal RADE is a row address decode signal for activating a row address decoder, a signal RXT is a word line trigger signal for indicating an activation timing of a word line, a signal REFA is a clock signal for allowing counting of an address during the auto-refresh operation, and a signal Q is an address signal of a refresh operation that is internally generated. Moreover, a signal WL is a signal supplied to a word line, a signal S0N is a sense amplifier activating signal, and signals BL and ZBL are signals supplied to a bit line.
In addition, the prefix xe2x80x9cZxe2x80x9d attached to a signal indicates that the signal is an L-active signal.
A command is acknowledged at time t1 at a rising edge of a clock signal ext.CLK. At time t1, signals ZCS, ext.ZRAS, and ext.ZCAS are all set to the logic low or L level, while signals ext.ZWE and CKE are set to the H level.
According to these signals, node N11 of FIG. 17 changes to the L level, and accordingly, node N12 is set to the H level. Consequently, latch circuit 704 is set so that signal AREFS is set to the H level.
Thereafter, when node N13 changes to the H level after being delayed for the delay time of inversion delay circuit 698, node N12 is accordingly set to the L level, but latch circuit 704 is still set, so that auto-refresh signal AREF is maintained at the H level.
When auto-refresh signal AREF is set to the H level, 1 shot pulse generating circuit 584 shown in FIG. 15 is rendered active and an H pulse is generated in a signal REFA. According to the H pulse generated in signal REFA, internal address counter 586 is activated, and counts one by one internal addresses Q for the refresh.
On the other hand, according to a clock edge at time t1, active command decoder 572 of FIG. 15 activates signal ACT. Accordingly, NOR circuit 558 of FIG. 15 activates signal ZRASE to the L level.
According to the change of signal ZRASE, control circuit 562 first activates signal RXT at time t1, and activates sense amplifier activating signal S0N at time t3 which is determined by an internal delay.
When signal RXT is set to the H level at time t2, a word line of the decoded address is selected, and a potential difference V0 corresponding to the data of a memory cell is generated between bit lines BL and ZBL.
At time t3, when the sense amplifier activating signal is set to the H level, a sense amplifier is activated, potential difference V0 between bit lines BL and ZBL is amplified, and a refresh operation is performed.
Then, when node N14 is set to the L level after the delay time of delay stage 706 of FIG. 17, node N15 changes to the H level, and auto-refresh signal AREF changes to the L level. Consequently, NOR circuit 558 of FIG. 15 sets signal ZRASE to the H level so that the refresh operation is terminated.
In the auto-refresh operation as described above, when a command is externally supplied, a refresh address is counted internally, and the refresh operation is performed once. Thus, there is no need to provide an address input for the refresh from outside.
Next, a self-refresh operation of the conventional DRAM will be described.
FIG. 19 is an operational waveform chart related to a description of an operation during the self-refresh operation of the conventional DRAM.
Referring to FIGS. 15 and 19, a self-refresh command is acknowledged at a rising edge of clock signal ext.CLK at time t2. The self-refresh command can be designated by setting signals ZCS, ext.ZRAS, ext.ZCAS, and CKE at the L level and setting signal ext.ZWE at the H level.
Thus, self-refresh command decoder 576 of FIG. 15 activates a signal SREF to the H level. Accordingly, self-refresh timer 580 is activated, and sets signal RINGOUT to the H level for a certain time period.
Consequently, auto-refresh signal AREF is set to the H level for a certain time period, and the refresh operation is performed as in the case described with reference to FIG. 18.
At time t3 when a certain time period has passed since signal ZRASE was set to the L level, self-refresh timer 580 sets signal RINGOUT to the L level. At time t4 when an additional time period has passed, self-refresh timer 580 sets signal RINGOUT to the H level. In this manner, signal RINGOUT is alternately set to the L level and the H level at certain intervals.
According to signal RINGOUT, auto-refresh signal AREF is set to the L level and the H level at certain intervals in a similar manner so that the refresh operation is performed automatically while the row address is successively counted.
In the self-refresh operation as described above, when a command is externally supplied, the refresh address is counted internally, and the refresh operation is performed repeatedly.
As described above, the DRAM is required to perform a refresh operation at certain intervals so as to prevent written data from being lost. The DRAM consumes power every time the refresh operation is performed.
In recent years, a large capacity memory is being mounted on a personal digital assistant and the like, and a further reduction in power consumption is demanded of a DRAM used in such products.
In the conventional DRAM, however, the row activation control is performed in a refresh operation at timing similar to that in a normal read operation so that there is a problem of large power consumption during the refresh operation.
The object of the present invention is to provide a semiconductor memory device capable of achieving reduction and power consumption during a refresh operation.
The present invention, in short, is provided with a memory block including a plurality of memory cells arranged in a matrix of rows and columns, and a control circuit.
The memory block includes a plurality of word lines corresponding to the rows, a plurality of bit line pairs corresponding to the columns, a row decode circuit for selectively activating a part of the plurality of word lines, a column decode circuit for selecting a part of the plurality of bit line pairs, and a sense amplifier circuit for amplifying data read on the plurality of bit lines.
The control circuit controls the row decode circuit and the sense amplifier circuit. The control circuit includes a command decode circuit for detecting a plurality of commands from a control signal externally supplied, and a row activation timing control unit for outputting a first activating signal that indicates an activation timing of a word line and a second activating signal that indicates an activation timing of the sense amplifier circuit according to an output from the command decode circuit.
The row activation timing control unit activates the first activating signal, and after a first delay time, activates the second activating signal when a command detected by the command decode circuit is a first command. The row activation timing control unit activates the first activating signal, and after a second delay time which is longer than the first delay time, activates the second activating signal when the command detected by the command decode circuit is a second command.
According to another aspect of the present invention, the semiconductor memory device is provided with a plurality of memory blocks and a control circuit.
Each of the plurality of memory blocks includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines corresponding to the rows, a plurality of bit line pairs corresponding to the columns, a row decode circuit for selectively activating a part of the plurality of word lines, a column decode circuit for selecting a part of the plurality of bit line pairs, and a sense amplifier circuit for amplifying data read on the plurality of bit lines.
The control circuit controls the row decode circuit and the sense amplifier circuit. The control circuit includes a command decode circuit for detecting a plurality of commands from a control signal externally supplied, and a plurality of row activation timing control units for outputting a first activating signal that indicates an activation timing of a word line and a second activating signal that indicates an activation timing of the sense amplifier circuit according to an output from the command decode circuit.
Each of the plurality of row activation timing control units activates the first activating signal, and after a first delay time, activates the second activating signal when a command detected by the command decode circuit is a first command, while it activates the first activating signal, and after a time period longer than the first delay time, activates the second activating signal when the command detected by the command decode circuit is a second command.
The respective time periods from the activation of the first activating signal to the activation of the second activating signal according to the second command are different for the plurality of row activation timing control units.
Therefore, the principal advantage of the present invention is that power consumption can be reduced during an operation according to the second command.
Another advantage of the present invention lies in that, since the activation timing of the sense amplifier is shifted for the respective memory blocks, a peak value of the consumed current can be made small, thereby achieving further reduction in power consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.